Computer systems and other electronic systems rely on the communication of digital data. Synchronous Dynamic Random Access Memory (SDRAM) devices are commonly used in computer systems, and such SDRAM devices cooperate with processor devices to support data read and write operations. The JEDEC Solid State Technology Association publishes specifications related to double data rate (DDR) SDRAM devices. The existing DDR specifications are the DDR2 and DDR3 specifications. According to DDR2/DDR3, the SDRAM memory cells transfer data on both rising and falling clock edges. DDR2 devices support 4-bit or 8-bit output burst modes, while DDR3 devices support an 8-bit output burst mode.
In a read operation, a DDR2/DDR3 device generates a clock/strobe signal (referred to as DQS) and data signals (referred to as DQ). Each byte includes eight single-ended DQ signals and one or two differential DQS signals. In one operating mode, one differential DQS signal is used to clock the eight DQ signals in a byte. In another operating mode, one differential DQS signal is used to clock four DQ signals in a byte, while a second differential DQS signal is used to clock the other four DQ signals in the byte. Ideally, the memory device outputs the DQ and DQS signals for a given byte in a time-aligned (e.g., edge-aligned) manner. However, the edges may no longer be aligned by the time the DQ and DQS signals reach the processor. In other words, the DQ signals will typically be skewed relative to one another when they arrive at the processor. Excessive skew in the DQ signals can make it difficult to clock all of them using one DQS signal because of an increased likelihood of sampling a DQ signal while it is transitioning between valid states, and excessive skew limits the maximum DDR operating speed.